Provides AXI-Lite register read/write access to the FPGA.
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virtual ErrorCode | Read (UINT64 address, UINT32 *pBuffer, std::size_t count, UINT32 timeoutMilliseconds, UINT64 &transferByteCount)=0 |
| | Read multiple 32-bit registers starting at the given address.
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virtual ErrorCode | Write (UINT64 address, const UINT32 *pData, std::size_t count, UINT32 timeoutMilliseconds, okTOperationStatistics &operationStats)=0 |
| | Write multiple 32-bit registers starting at the given address.
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virtual ErrorCode | Reset (void)=0 |
| | Reset the AXI-Lite interface.
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ErrorCode | Read (UINT64 address, UINT32 &value, UINT32 timeoutMilliseconds, UINT64 &transferByteCount) |
| | Read a single register with an explicit timeout.
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ErrorCode | Write (UINT64 address, UINT32 value, UINT32 timeoutMilliseconds, okTOperationStatistics &operationStats) |
| | Write a single register with an explicit timeout.
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ErrorCode | Read (UINT64 address, UINT32 *pBuffer, std::size_t count, UINT64 &transferByteCount) |
| | Read multiple registers using the default timeout.
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ErrorCode | Write (UINT64 address, const UINT32 *pData, std::size_t count, okTOperationStatistics &operationStats) |
| | Write multiple registers using the default timeout.
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ErrorCode | Read (UINT64 address, UINT32 &value) |
| | Read a single register using the default timeout.
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ErrorCode | Write (UINT64 address, UINT32 value) |
| | Write a single register using the default timeout.
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This interface provides 32-bit register-level access to the FPGA over the AXI-Lite protocol. It supports single-register and multi-register (bulk) read and write operations.
An instance of this class is obtained via okCFPGADataPortAXI::GetAXILite().
- Note
- AXI data port support will be available in a future release. No currently supported devices provide this interface.
