Provides AXI-Full memory-mapped read/write access to the FPGA.
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virtual UINT8 | GetDatapathWidthByteCount (void) const =0 |
| | Returns the datapath width in bytes.
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virtual ErrorCode | Read (UINT64 address, unsigned char *pBuffer, std::size_t bufferSize, UINT32 burst, UINT32 timeoutMilliseconds, UINT64 &transferByteCount)=0 |
| | Read data from the given address.
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virtual ErrorCode | Write (UINT64 address, const unsigned char *pData, std::size_t dataSize, UINT32 burst, UINT32 timeoutMilliseconds, okTOperationStatistics &operationStats)=0 |
| | Write data to the given address.
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virtual ErrorCode | Reset (void)=0 |
| | Reset the AXI-Full interface.
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ErrorCode | Read (UINT64 address, unsigned char *pBuffer, std::size_t bufferSize, UINT64 &transferByteCount) |
| | Read data using the default burst length and timeout.
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ErrorCode | Write (UINT64 address, const unsigned char *pData, std::size_t dataSize, okTOperationStatistics &operationStats) |
| | Write data using the default burst length and timeout.
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This interface provides byte-level, burst-capable access to the FPGA over the AXI-Full protocol. It supports configurable burst lengths and variable datapath widths.
An instance of this class is obtained via okCFPGADataPortAXI::GetAXIFull().
- Note
- AXI data port support will be available in a future release. No currently supported devices provide this interface.
